An FPGA implementation of a high resolution phase shift beamformer

Abstract

In this work, an implementation of a high resolution phase shift beamformer on FPGA is presented. This implementation is based on the angle recording (AR) CORDIC algorithm and uses a fine precision 2-path floating point adder for an accurate computation of the phase shifts. A pipelined architecture is used to decrease the chip area requirements and to increase the throughput of the beamformer. The proposed approach is quantitatively evaluated by performing a comparison with am approach based on the Xilinx core generator modules. The results show that the proposed implementation outperforms the latter technique in terms of speed and area. The implemented beamformer could be used for acquiring 2D and 3D ultrasound medical images in real time.