Please use this identifier to cite or link to this item:
Title: Non-refreshing analog neural storage tailored for on-chip learning
Authors: Halabi, Bassem Al
Malluhi, Qutaibah
Ayoubi, Rafic 
Affiliations: Department of Computer Engineering 
Keywords: Analogue processing circuits
Analogue storage
Neural chips
Subjects: VLSI (Technology)
Issue Date: 2002
Publisher: IEEE
Part of: Proceedings of the 8th Great Lakes Symposuim on VLSI
Conference: Great Lakes Symposium on VLSI (8th : 21-21 Feb. 1998 : Lafayette, LA, USA) 
In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally update the weights from the analog back-propagation signals for fast on-chip learning. In this circuit, the weight is stored as a 5-bit digital number, which controls the gates of five pass transistors allowing five binary-weighted (1,2,4,8,16) voltage references to integrate at a voltage adder. The output of the voltage adder is the analog weight. The 5-bit register is designed as an up/down counter so that every pulse on the up/down input will increase/decrease the weight by one level out of 32 possible levels. The learning circuit takes the analog graded error signal and generates two pulse streams for up/down counting depending on the sign of the error signal. The duration of the pulse stream is proportional to the magnitude of the error signal. This complete modular synaptic body (storage and learning technique) is appropriate for large scaleable analog VLSI neural networks because it handles recall and learning operations at the same speed with full parallelism.
Ezproxy URL: Link to full text
Type: Conference Paper
Appears in Collections:Department of Computer Engineering

Show full item record

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.