Hardware architecture for a bit-serial odd-even transposition sort network with on-the-fly compare and swap

Abstract

Sorting algorithms are computationally expensive routines frequently executed on modern computers and embedded systems. Implementing sorting algorithms on dedicated hardware can contribute significantly to the overall execution time of the processes and applications embodying them. However, such algorithms are known to suffer from a trade off between convergence time and computational complexity. Consequently, this causes performance degradation i.e. bottleneck, when implemented on dedicated hardware with limited resources. In this respect, this paper proposes a novel sequential hardware architecture for a bit-serial Odd-Even transposition sorting network with on-the-fly compare and swap, on field programmable gate array (FPGA). In contrast to the classical parallel-data architecture, which operates on N data bits, this implementation significantly minimizes resource utilization while offering higher clock frequency, on the fly compare and swap and preserving O(N) performance complexity. Simulation and synthesis results demonstrates that the proposed architecture is parallel, minimal in size, can operate on much larger arrays for a reference area size, can be easily expanded, and can achieve higher operating frequency.