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|Title:||FPGA design of spatially modulated single-input-multiple-output signals in 5G diversity receivers||Authors:||Ayoubi, Rafic
Daba, Jihad S.
|Affiliations:||Department of Computer Engineering
Department of Electrical Engineering
|Subjects:||Field programmable gate arrays||Issue Date:||2019||Publisher:||IEEE||Part of:||2019 IEEE International Conference on Communication, Networks and Satellite (Comnetsat)||Conference:||IEEE International Conference on Communication, Networks and Satellite (Comnetsat) (1-3 Aug 2019 : Makassar, Indonesia)||Abstract:||
In this work, FPGA implementation of a new optimal generalized receiver diversity combining scheme, termed Generalized Maximum Ratio Combining (GMRC), is implemented for transmission via 5G multiple-input-multiple-output (MIMO) channels. The MIMO channels comprise binary phase shift keying-spatially modulated (BPSK-SM) single-input-multiple-output (SIMO) channels that are conceived from robust selective combining of transmit diversity channels. The main disadvantage of GMRC is the fundamental nature of its analysis, which prompts us to investigate the feasibility of a FPGA implementation using a pipeline structure. Such implementation can serve as a practical test-bed for real-life wireless applications. Prior published FPGA implementation applied brute-force technique that led to the use of several square root blocks, which are slow and resource-hungry. In this work, all operations are transformed into addition and multiplication operations only, which are efficient in current FPGA technology due to the availability of such operations at the hardware level. Another important feature of the implementation is pipelining, which further leads to an improved clock cycle and subsequently higher throughput. Using the FPGA implementation on the SIMO channel, the design can be extended to the hardware of spatially modulated hyper-MIMO based 5 th generation networks.
|URI:||https://scholarhub.balamand.edu.lb/handle/uob/571||Ezproxy URL:||Link to full text||Type:||Conference Paper|
|Appears in Collections:||Department of Computer Engineering|
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