Please use this identifier to cite or link to this item:
Title: An efficient implementation of multi-layer perceptron on mesh architecture
Authors: Ayoubi, Rafic 
Bayoumi, Magdy A.
Affiliations: Department of Computer Engineering 
Keywords: Neural net architecture
Multilayer perceptrons
Parallel architectures
Issue Date: 2002
Part of: 2002 IEEE International Symposium on Circuits and Systems (ISCAS)
Conference: IEEE International Symposium on Circuits and Systems (26-29 May 2002 : Phoenix-Scottsdale, AZ, USA) 
This paper presents a new efficient parallel implementation of multi-layer perceptron on mesh-connected SIMD machines. A new algorithm to implement the recall and training phases of the multi-layer perceptron network with back-error propagation is devised. The developed algorithm is much faster than other known algorithms of its class and comparable in speed to more complex architecture such as hypercube without the added cost; it requires O(1) multiplications and O(log N ) additions, whereas most others require O(N) multiplications and O(N) additions. The proposed algorithm maximizes parallelism by unfolding the ANN computation to its smallest computational primitives and processes these primitives in parallel.
Ezproxy URL: Link to full text
Type: Conference Paper
Appears in Collections:Department of Computer Engineering

Show full item record

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.