Please use this identifier to cite or link to this item: https://scholarhub.balamand.edu.lb/handle/uob/4965
Title: Two stages parallel LMS structure: A pipelined hardware architecture
Authors: Akkad, G.
Mansour, Ali
ElHassan, Bachar
Inaty, Elie 
Ayoubi, Rafic 
Keywords: LMS
Parallel LMS
Relaxed Look-Ahead
FPGA
Antenna array
Adaptive Beamforming
Issue Date: 2021
Part of: Institute of Electrical and Electronics Engineers
Start page: 2363
End page: 2367
Conference: 28th European Signal Processing Conference (EUSIPCO)
Abstract: 
© 2021 European Signal Processing Conference, EUSIPCO. All rights reserved. Modern wireless communication systems have tighten the requirements of adaptive beamformers when implemented on Field Programmable Gate Array (FPGA). The set requirements imposed additional constraints such as designing a high throughput, low complexity system with fast convergence and low steady state error. Recently, a parallel multi-stage least mean square (pLMS) structure is proposed to mitigate the listed constraints. pLMS is a two stages least mean square (LMS) operating in parallel and connected by an error feedback. To form the total pLMS error, the second LMS stage (LMS2) error is delayed by one sample and fed-back to combine with that of the first LMS stage (LMS1). pLMS provides accelerated convergence while maintaining minimal steady state error and a computational complexity of order O(N), where N represent the number of antenna elements. However, pipelining the pLMS structure is still difficult due to the LMS coefficient update loop. Thus, in this paper, we propose the application of the delay and sum relaxed look ahead technique to design a high throughput pipelined hardware architecture for the pLMS. Hence, the delayed pLMS (DpLMS) is obtained. Simulation and synthesis result, highlight the superior performance of the DpLMS in presenting a high throughput architecture while preserving accelerated convergence, low steady state error and low computational complexity. DpLMS operates at a maximum frequency of 208.33 MHz and is obtained at the cost of a marginal increase in resource requirements, i.e. additional delay registers compared to the original pLMS design.
URI: https://scholarhub.balamand.edu.lb/handle/uob/4965
ISBN: 9789082797053
ISSN: 22195491
DOI: 10.23919/Eusipco47968.2020.9287770
Ezproxy URL: Link to full text
Type: Conference Paper
Appears in Collections:Department of Computer Engineering

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