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|Title:||Design and realization of analog Phi-function for LDPC decoder||Authors:||Baker, A
Bayoumi, Magdy A.
|Affiliations:||Department of Computer Engineering||Keywords:||Table lookup
Parity check codes
|Subjects:||Logic design||Issue Date:||2007||Publisher:||IEEE||Part of:||2007 IEEE International Symposium on Circuits and Systems||Conference:||IEEE International Symposium on Circuits and Systems (27-30 May 2007 : New Orleans, LA, USA)||Abstract:||
One of the ambitious design goals of future generations of wireless systems, including 4G, IEEE 802.11n/802.16 standards, is to reliably provide very high data rate transmission in real-time. This poses a challenge to find an optimal coding scheme that has good performance and can be efficiently implemented in hardware. The most well-known LDPC decoding algorithm is log sum product (log-SP) in which a set of calculations on a non-linear function called Phi-function is approximated by a minimum function. Until now this function has been implemented through look up tables (LUT). But this direct implementation is costly for hardware. Also LUTs are very sensitive to the number of quantization bits and number of LUT values. Therefore, we have proposed analog Phi-function. The design is easily scalable and reconfigurable for larger block sizes. Simulation results show that our proposed design dissipates only 18 nW.
|URI:||https://scholarhub.balamand.edu.lb/handle/uob/479||Ezproxy URL:||Link to full text||Type:||Conference Paper|
|Appears in Collections:||Department of Computer Engineering|
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