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dc.contributor.authorBaker, Aen_US
dc.contributor.authorGhosh, Soumiken_US
dc.contributor.authorKumar, Ashoken_US
dc.contributor.authorBayoumi, Magdy A.en_US
dc.contributor.authorAyoubi, Raficen_US
dc.description.abstractOne of the ambitious design goals of future generations of wireless systems, including 4G, IEEE 802.11n/802.16 standards, is to reliably provide very high data rate transmission in real-time. This poses a challenge to find an optimal coding scheme that has good performance and can be efficiently implemented in hardware. The most well-known LDPC decoding algorithm is log sum product (log-SP) in which a set of calculations on a non-linear function called Phi-function is approximated by a minimum function. Until now this function has been implemented through look up tables (LUT). But this direct implementation is costly for hardware. Also LUTs are very sensitive to the number of quantization bits and number of LUT values. Therefore, we have proposed analog Phi-function. The design is easily scalable and reconfigurable for larger block sizes. Simulation results show that our proposed design dissipates only 18 nW.en_US
dc.subjectTable lookupen_US
dc.subjectIEEE standardsen_US
dc.subjectParity check codesen_US
dc.subject.lcshLogic designen_US
dc.titleDesign and realization of analog Phi-function for LDPC decoderen_US
dc.typeConference Paperen_US
dc.relation.conferenceIEEE International Symposium on Circuits and Systems (27-30 May 2007 : New Orleans, LA, USA)en_US
dc.contributor.affiliationDepartment of Computer Engineeringen_US
dc.relation.ispartoftext2007 IEEE International Symposium on Circuits and Systemsen_US
Appears in Collections:Department of Computer Engineering
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