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|Title:||Constant Time Hardware Architecture for a Gaussian Smoothing Filter||Authors:||Akkad, Ghattas
|Affiliations:||Department of Computer Engineering
Department of Computer Engineering
Department of Electrical Engineering
|Subjects:||Image processing||Issue Date:||2019||Publisher:||IEEE||Part of:||International Conference on Signal Processing and Information Security (ICSPIS)||Start page:||1||End page:||4||Conference:||International Conference on Signal Processing and Information Security (ICSPIS) (7-8 Nov 2018 : DUBAI, United Arab Emirates)||Abstract:||
In this paper a new and highly efficient hardware architecture for a bit-serial implementation of a 3*3 filter on FPGA is developed and presented. The concept is implemented on a Gaussian blur spatial filter and it can be extended to other filters with similar characteristics. The proposed Single Instruction Multiple Data (SIMD) architecture provides a constant operating time independent of the size of the given image while the arithmetic operations are limited to the operations of addition. The Multiple Instruction Multiple Data (MIMD) performance is achieved in a near fraction of the cost. Thus, the hardware's utilization is optimized. The total time needed to perform the filter of interest on the given image is solely dependent on the working clock frequency. The proposed design is evaluated using a small image and is implemented on two FPGA families with various sizes of an image. Also, it is compared with other architectures.
|URI:||https://scholarhub.balamand.edu.lb/handle/uob/461||Ezproxy URL:||Link to full text||Type:||Conference Paper|
|Appears in Collections:||Department of Computer Engineering|
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