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|Title:||Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs||Authors:||Clemente, Juan Antonio
El Falou, Wassim
|Affiliations:||Department of Computer Engineering||Keywords:||Artificial Neural Network (ANN)
Hopfield Neural Network (HNN)
Single Event Upset (SEU)
Single Event Transient (SET)
|Subjects:||FPGA||Issue Date:||2016||Part of:||Journal of neurocomputing||Volume:||171||Start page:||1606||End page:||1609||Abstract:||
This letter presents an FPGA implementation of a fault-tolerant Hopfield Neural Network (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non-fault-tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.
|URI:||https://scholarhub.balamand.edu.lb/handle/uob/2058||DOI:||10.1016/j.neucom.2015.06.038||Ezproxy URL:||Link to full text||Type:||Journal Article|
|Appears in Collections:||Department of Computer Engineering|
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