Please use this identifier to cite or link to this item:
https://scholarhub.balamand.edu.lb/handle/uob/2058
Title: | Hardware implementation of a fault-tolerant hopfield neural network on FPGAs | Authors: | Clemente, Juan Antonio Mansour, Wassim Ayoubi, Rafic Serrano, Felipe Mecha, Hortensia Ziade, Haissam El Falou, Wassim Velazc, Raoul |
Affiliations: | Department of Computer Engineering | Keywords: | Artificial Neural Network (ANN) Hopfield Neural Network (HNN) Single Event Upset (SEU) Single Event Transient (SET) Fault tolerance |
Subjects: | FPGA | Issue Date: | 2016 | Part of: | Journal of neurocomputing | Volume: | 171 | Start page: | 1606 | End page: | 1609 | Abstract: | This letter presents an FPGA implementation of a fault-tolerant Hopfield Neural Network (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non-fault-tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design. |
URI: | https://scholarhub.balamand.edu.lb/handle/uob/2058 | DOI: | 10.1016/j.neucom.2015.06.038 | Ezproxy URL: | Link to full text | Type: | Journal Article |
Appears in Collections: | Department of Computer Engineering |
Show full item record
SCOPUSTM
Citations
25
checked on Nov 16, 2024
Record view(s)
74
checked on Nov 17, 2024
Google ScholarTM
Check
Altmetric
Altmetric
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.