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Please use this identifier to cite or link to this item: https://scholarhub.balamand.edu.lb/handle/uob/2058
DC FieldValueLanguage
dc.contributor.authorClemente, Juan Antonioen_US
dc.contributor.authorMansour, Wassimen_US
dc.contributor.authorAyoubi, Raficen_US
dc.contributor.authorSerrano, Felipeen_US
dc.contributor.authorMecha, Hortensiaen_US
dc.contributor.authorZiade, Haissamen_US
dc.contributor.authorEl Falou, Wassimen_US
dc.contributor.authorVelazc, Raoulen_US
dc.date.accessioned2020-12-23T09:05:37Z-
dc.date.available2020-12-23T09:05:37Z-
dc.date.issued2016-
dc.identifier.urihttps://scholarhub.balamand.edu.lb/handle/uob/2058-
dc.description.abstractThis letter presents an FPGA implementation of a fault-tolerant Hopfield Neural Network (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non-fault-tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.en_US
dc.language.isoengen_US
dc.subjectArtificial Neural Network (ANN)en_US
dc.subjectHopfield Neural Network (HNN)en_US
dc.subjectSingle Event Upset (SEU)en_US
dc.subjectSingle Event Transient (SET)en_US
dc.subjectFault toleranceen_US
dc.subject.lcshFPGAen_US
dc.titleHardware implementation of a fault-tolerant hopfield neural network on FPGAsen_US
dc.typeJournal Articleen_US
dc.identifier.doi10.1016/j.neucom.2015.06.038-
dc.contributor.affiliationDepartment of Computer Engineeringen_US
dc.description.volume171en_US
dc.description.startpage1606en_US
dc.description.endpage1609en_US
dc.date.catalogued2018-01-10-
dc.description.statusPublisheden_US
dc.identifier.ezproxyURLhttp://ezsecureaccess.balamand.edu.lb/login?url=https://doi.org/10.1016/j.neucom.2015.06.038en_US
dc.identifier.OlibID176010-
dc.relation.ispartoftextJournal of neurocomputingen_US
dc.provenance.recordsourceOliben_US
crisitem.author.parentorgFaculty of Engineering-
Appears in Collections:Department of Computer Engineering
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