FPGA realization of MRC with optimized exponent for adaptive array antennas

Abstract

In this work, a fast FPGA implementation of an optimized receiver diversity combining technique, termed Generalized Maximal Ratio Combining (GMRC), is implemented for signal transmission over wireless Single-Input-Multiple-Output (SIMO) fading channels. One prior published FPGA implementation applied brute-force technique that led to the use of several square root blocks, which are slow and resource-hungry. A subsequent study improved the implementation by transforming all the operations into addition and multiplication only, which are efficient in current FPGA technology due to the availability of such operations at the hardware level. In this study, the proposed hardware implementation was more efficient and outperformed previous techniques both in terms of speed and area. In addition, a higher clock frequency of around 180 MHz was achieved. This high speed was possible due to sub-dividing the complex operations into smaller computation stages and pipelining all the stages. A prominent feature of the implementation is the use of a pipeline architecture to decrease the chip area requirements and to increase the throughput of the diversity combiner. Using the FPGA implementation on the SIMO channel, the design can be extended to the hardware of spatially modulated massive-MIMO in 5th generation networks.