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Title: FPGA hardware architecture for stereoscopic image compression based on block matching, watermarking and hamming code
Authors: Akkad, Ghattas
Hassan, Moustapha El 
Ayoubi, Rafic 
Affiliations: Department of Computer Engineering 
Department of Electrical Engineering 
Department of Computer Engineering 
Keywords: Data compression--Data compression--Data compression
Hamming codes
Image coding
Image watermarking
Stereo image processing
Subjects: Field programmable gate arrays
Issue Date: 2016
Publisher: IEEE
Part of: 2016 International Image Processing, Applications and Systems (IPAS)
Conference: International Image Processing, Applications and Systems Conference (5-7 November 2016 : Hammamet, Tunisia) 
Image compression and size reduction increases the number of images stored on a memory space and reduces bandwidth consumption while increasing transmission speed on a communication channel. Images can be compressed and decompressed using different methods and algorithms. With the vast increase of quality and size, dedicated processors with parallel processing blocks such as FPGAs are mainly targeted to implementing faster processing circuits and algorithms. This paper proposes FPGA hardware architecture for a stereoscopic image compression algorithm based on block matching, watermarking and Hamming code.
DOI: 10.1109/IPAS.2016.7880065
Ezproxy URL: Link to full text
Type: Conference Paper
Appears in Collections:Department of Computer Engineering

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