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|Title:||FFT Radix-2 and Radix-4 FPGA Acceleration Techniques Using HLS and HDL for Digital Communication Systems||Authors:||Akkad, Ghattas
Hassan, Bachar El
Frederic , Le Roy
|Affiliations:||Department of Computer Engineering||Keywords:||FFT
|Subjects:||VHDL (Computer hardware description language)
Verilog (Computer hardware description language)
|Issue Date:||2018||Part of:||2018 IEEE International Multidisciplinary Conference on Engineering Technology (IMCET)||Start page:||1||End page:||5||Conference:||Multidisciplinary Conference on Engineering Technology (IMCET) (14-16 Nov 2018 : Beirut, Lebanon)||Abstract:||
Fast Fourier Transform (FFT) is generally implemented on reconfigurable hardware in several signal processing or digital communication applications. It can be considered the most time and resource consuming operations due to the need of complex operations. The main of this manuscript is to investigate the contribution of High Level Synthesis (HLS) techniques on the implementation of real time FFT algorithms using field programmable gate arrays (FPGAs). In particular, this study focuses on communication systems incorporating filter-based-multicarrier modulations (FBMC), a promising candidate for the 5G technology. In order to evaluate the contribution of HLS, we implemented and tested various combinations such as: 8 and 16 points radix-2 and radix-4 FFT using finite precision, HLS tools and HDL while prompting parallelization, pipelining and hardware reuse architectures.
|URI:||https://scholarhub.balamand.edu.lb/handle/uob/563||Ezproxy URL:||Link to full text||Type:||Conference Paper|
|Appears in Collections:||Department of Computer Engineering|
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