Please use this identifier to cite or link to this item: https://scholarhub.balamand.edu.lb/handle/uob/600
DC FieldValueLanguage
dc.contributor.authorAyoubi, Raficen_US
dc.contributor.authorIstambouli, Sameren_US
dc.contributor.authorAbbas, Abdulwaheden_US
dc.contributor.authorAkkad, Ghattasen_US
dc.date.accessioned2020-12-23T08:33:15Z-
dc.date.available2020-12-23T08:33:15Z-
dc.date.issued2019-
dc.identifier.urihttps://scholarhub.balamand.edu.lb/handle/uob/600-
dc.description.abstractSorting is one of the most frequently executed routines on modern computers. Such algorithms are classically implemented as software programs and can contribute significantly to the overall execution time of a process. In this respect, implementing sorting algorithms in hardware can dramatically increase the overall performance of the applications embodying them. This paper proposes an optimized hardware architecture for a parallel Odd-Even transposition sorting network, on field programmable gate array (FPGA) based embedded systems. This implementation introduces a modification of the classical Odd-Even Transposition sorting algorithm. This modification is a shift-based approach offering high flexibility for general purpose applications. The proposed architecture results in increasing overall performance by minimizing hardware resource utilization, increasing the operating frequency and reducing complexity. Simulation and synthesis results demonstrates that the proposed architecture is minimal in size, can operate on odd and even length arrays, capable of sorting arrays of length larger than two times the number of available processors, and can begin the sorting process at data input.en_US
dc.format.extent6 p.en_US
dc.language.isoengen_US
dc.subjectSortingen_US
dc.subjectOdd-Even Transpositionen_US
dc.subjectHardware Architectureen_US
dc.subjectFPGAen_US
dc.subjectLow Latencyen_US
dc.subject.lcshEmbedded systems (Computer systems)en_US
dc.titleHardware Architecture For A Shift-Based Parallel Odd-Even Transposition Sorting Networken_US
dc.typeConference Paperen_US
dc.relation.conferenceInternational Conference on Advances in Computational Tools for Engineering Applications (ACTEA) (4th : 3-5 July 2019 : Beirut, Lebanon)en_US
dc.contributor.affiliationDepartment of Computer Engineeringen_US
dc.contributor.affiliationDepartment of Computer Scienceen_US
dc.contributor.affiliationDepartment of Computer Engineeringen_US
dc.description.startpage1en_US
dc.description.endpage6en_US
dc.date.catalogued2020-02-18-
dc.description.statusPublisheden_US
dc.identifier.ezproxyURLhttp://ezsecureaccess.balamand.edu.lb/login?url=https://ieeexplore.ieee.org/document/8851099en_US
dc.identifier.OlibID252451-
dc.relation.ispartoftext2019 Fourth International Conference on Advances in Computational Tools for Engineering Applications (ACTEA)en_US
dc.provenance.recordsourceOliben_US
Appears in Collections:Department of Computer Engineering
Show simple item record

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.