Please use this identifier to cite or link to this item:
https://scholarhub.balamand.edu.lb/handle/uob/558
DC Field | Value | Language |
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dc.contributor.author | Ayoubi, Rafic | en_US |
dc.contributor.author | Ziade, Haissam | en_US |
dc.contributor.author | Bayoumi, Magdy A. | en_US |
dc.date.accessioned | 2020-12-23T08:32:28Z | - |
dc.date.available | 2020-12-23T08:32:28Z | - |
dc.date.issued | 2003 | - |
dc.identifier.uri | https://scholarhub.balamand.edu.lb/handle/uob/558 | - |
dc.description.abstract | The associative Hopfield memory, is a very useful artificial neural network (ANN) that can be utilized in numerous applications. Examples include, pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper provides an efficient and fault tolerant algorithm for implementing the Hopfield ANN on a torus parallel architecture. The main advantage of this algorithm is fault tolerance, high performance, and cost effectiveness. The developed algorithm is much faster than other known algorithms of its class and comparable in speed to more complex architectures such as the hypercube without the added cost. It requires O(1) multiplications and O(log N) additions, whereas most others require O(N) multiplications and O(N) additions. Moreover, the developed algorithm has an added advantage over other known algorithms due to its fault tolerance feature, which is based on ABFT techniques. The main advantage of our ABFT (algorithm-based fault tolerance) method over other existing ABFT methods is its ability to detect and correct several faults without any additional hardware overhead (i.e. no extra row or column is needed). | en_US |
dc.language.iso | eng | en_US |
dc.publisher | IEEE | en_US |
dc.subject | Digital arithmetic | en_US |
dc.subject | Hopfield neural nets | en_US |
dc.subject | Fault tolerance | en_US |
dc.subject | Content-addressable storage | en_US |
dc.subject | Parallel architectures | en_US |
dc.title | Fault tolerant hopfield associative memory on torus | en_US |
dc.type | Conference Paper | en_US |
dc.relation.conference | IEEE Symposium on Defect and Fault Tolerance in VLSI Systems (18th : 5-5 Nov. 2003 : Boston, MA, USA, USA) | en_US |
dc.contributor.affiliation | Department of Computer Engineering | en_US |
dc.date.catalogued | 2018-01-11 | - |
dc.description.status | Published | en_US |
dc.identifier.ezproxyURL | http://ezsecureaccess.balamand.edu.lb/login?url=http://ieeexplore.ieee.org/document/1250133/ | en_US |
dc.identifier.OlibID | 176322 | - |
dc.relation.ispartoftext | Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems | en_US |
dc.provenance.recordsource | Olib | en_US |
crisitem.author.parentorg | Faculty of Engineering | - |
Appears in Collections: | Department of Computer Engineering |
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